Transient Worst Case Analysis: Why?

Have you ever tried to use a transistor for a power application? You could choose a 20A MOSFET to switch a 2A supply line and say:

“It’s not necessary to compute worst case analyses because my transistor is ten times oversized!”

In fact your transistor is ten times oversized for static analysis with a dissipated power of about 125mW. But for your application, you need to analyze the transient effect of commutation.

When VGS grows, ID also increases, while VDS decreases.

The transient dissipated power of the transistor is defined by PTransistor = VDS x ID.

In static, when the commutation is over, PTransistor = 125mW (0.0625 x 2).

However power dissipation increases considerably during the commutation time. If this period is too long the transistor will be damaged.

In this example, the dissipated power will be over 2W, the mean power during the commutation will be 1.75W during 6ms. That’s much greater than the static values.

What about the worst case analysis of this transient power dissipation? By hand it is very difficult to evaluate.

Moreover, you have to crosscheck with the limitation of the transistor given by the datasheet. You can find this kind of graph is a transistor’s datasheet:

You have to report the previously computed value in the graph, in order to get the effective transient resistance. Knowing the power, you can deduct the temperature elevation and check if it fits with the datasheet limits.

It’s a long process, with several steps to accomplish the analysis…

Interested to have such values automatically computed for you? Stay tuned for the Raphton future releases!